1. Technical Field of the Invention
This invention relates to a process for making integrated circuit structures having a plurality of metallization layers. More particularly, this invention relates to an improved process of planarization to smooth an insulation layer placed between metallization layers.
2. Description of the Prior Art
In the production of integrated circuit structures, it has become increasingly important to provide structures having a plurality of metallization layers due to the ever increasing density of the circuit elements in the structure. To provide overlying metallization layers without discontinuities or other flaws, it is desirous to provide an underlying surface for the metallization layer which is as flat or planar as possible. This may be accomplished using doped glass which is subsequently heated to its softening point to provide smoother step coverage and more planar surface beneath the subsequent metallization layer. However, the application of heat to an integrated circuit structure to soften a doped glass becomes undesirable.
It has, therefore, become the practice to smooth the surface of an insulation layer in preparation for a subsequently applied metallization layer by a process of planarization. An insulation material, such as an oxide, is applied over the first metallization layer followed by application of another etchable material which can be easily removed after the etching such as a layer of photoresist. The insulation and photoresist are then subjected to a dry etch, such as an isotropic reactive ion etch. The dry etch removes a portion of the photoresist as well as the raised portions of the underlying insulation. The photoresist is then selectively removed to provide a smoother underlying surface having better step coverage. If the planarization is still not as smooth as desired, the prior art approach uses a thicker insulation layer and then a deeper etch back of the raised portions of the insulation.
However, the advent of newer integrated circuit technology, using reduced metal pitch as well as reduced spacing between metal lines, has made the use of such thick insulation layers to achieve better planarization counterproductive. The use of such thick insulation layers can result in the formation of voids adjacent the bottom of the narrow openings in the metallization layer due to the tendency of the deposited insulation material, such as an oxide, to deposit faster adjacent the top of the sidewalls of openings.
If such a void occurs, which is then covered up as further insulation material is applied, subsequent application of, for example, photoresist material would not be able to penetrate this void area. Subsequent etching would, therefore, remove the insulation covering the void thus exposing the void and, in essence, providing a nonplanar stepped area in diametric opposition to the attempted planarization. Furthermore, the insulation beneath the bottom portion of the now exposed void may be etched to thin the insulation over the underlying surface to an unacceptable thickness.
Quite surprisingly, it has now been discovered that the desired planarization can be achieved, even when smaller metal pitches and closer spacing between metal lines are used, without the risk of forming undesirable voids in the insulation layer.